As will be appreciated by the person of ordinary skill the art, understanding the functionality of an integrated circuit (IC), for example, a digital IC, starting from the finished device can be challenging. For example, modern digital IC designs are often created using a highly automated process. For instance, they are typically designed by writing a high level description of their function in a hardware description language which is then synthesized to the logic gate level. This approach, along with the increasing use of libraries of previously designed circuit sub-blocks (e.g. hard and/or soft “macros”) can enable the routine creation of a wide variety of gate designs.
The highly automated process, also known as auto-routing, often includes software programs that automatically place electrical components in a space efficient manner, which may not necessarily result in logically ordered or visually appealing circuit layouts. As a result, circuit elements representing the same functional block may have different layouts.
While IC reverse engineering technologies have been developed to recreate, with a reasonable degree of automation and accuracy, a low level netlist (otherwise known as gate, primitive or cell level netlists) of an IC, organization and analysis of these netlists into functional, modular and/or hierarchical blocks currently still heavily relies on substantial expert level human effort, which is not only highly time consuming, but can also be highly cost ineffective.
Different approaches have been developed in the art to provide automated logic extraction from ICs or functional identification of ICs. One approach, presented by Lester, A. Bazargan-Sabet, P. Greiner, A. in “YAGLE, a second generation functional abstractor for CMOS VLSI circuits”, Proceedings of the Tenth International Conference on Microelectronics, 1998, pages 265-268, (hereinafter “YAGLE”), is based on a functional abstraction method using a circuit disassembly procedure. YAGLE is primarily applicable to the abstraction of netlists to reduce their simulation time. It does not, however, provide human comprehensible results. Further, the approach in YAGLE is rather susceptible to netlist inaccuracies.
Another approach, presented by Boehner, M. in “LOGEX—an automatic logic extractor from transistor to gate level for CMOS technology”, Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, pages 517-522, provides a rule-based abstraction from transistor level to gate level. One of the shortcomings of this approach is its lack of a feasible rule-based approach for higher level abstraction at above the gate level.
Another known approach can be found in a publication by Ohlrich, M.; Ebeling, C.; Ginting, E.; and Sather, L. entitled “SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm”, Proceedings of the 30th international Design Automation Conference, 1993, pages 31-37. While SubGemini discussed in Ohlrich, M. et al. is one of the most significant algorithms in the field, it requires a completely known base library. As such, it is not well suited for high-level functional identification in view of modern optimization timing modification and synthesis techniques.
Therefore there remains a need for new IC analysis systems and methods that overcome some of the drawbacks of known approaches, or at least, provide a useful alternative to the public.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.